Experienced engineer manager with 18 years hardware architecture & design experience at -- high performance multicore CPU processor, telecom access network SoC with heterogenous multicore, CPU security, Tamper Resistant Hardware. Complete design flow from architecture roadmap, micro-archiecture design, front/backend design to tape out. Experienced on RISC-V, SPARC, X86, ARM, MIPS, CEVA, TENSILICA, AI accelerators and security enclaves.  Hold 5 approved patents on speculative memory prefetch & access, fast message passing memory/cache access.